To increase the integration degree of semiconductor memories, various memories having three-dimensional cells, including Bit Cost Scalable (BiCS) memories, have been suggested. Among these memories having three-dimensional cells, matrix channel stacked memories (MaCS) have been suggested as memories having three-dimensional cells, in which gate electrodes are embedded in a longitudinal direction and channel layers are laminated in a lateral direction.
The MaCSs read and write data in each cell as follows: a voltage is applied to the gate electrodes in a longitudinal direction to generate inversion layers around the gate electrodes; the generated inversion layers are interconnected to adjacent cells; and the interconnected inversion layers act as conduction paths of carriers (e− or h+) from bit lines to cells desired to be accessed. For each plurality of cells to which these conduction paths are formed (hereinafter, these cells are referred to as strings), contact regions, which connect the bit lines and each of the channel layers, are formed stepwise along a string direction so as to be connected to each of the laminated channel layers.
However, in the above structure, stepwise regions along the string direction are required at the outside of the cell regions for each one of the strings, and it is thus difficult to reduce the areas of the cell regions.